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DE1_TOP.asm.rpt
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Assembler report for DE1_TOP
Tue Jun 19 02:42:10 2018
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Encrypted IP Cores Summary
5. Assembler Generated Files
6. Assembler Device Options: D:/Electronics/MPU401 Core DE1/DE1_TOP.sof
7. Assembler Device Options: D:/Electronics/MPU401 Core DE1/DE1_TOP.pof
8. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Jun 19 02:42:10 2018 ;
; Revision Name ; DE1_TOP ;
; Top-level Entity Name ; DE1_TOP ;
; Family ; Cyclone II ;
; Device ; EP2C20F484C7 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Maximum processors allowed for parallel compilation ; All ; ;
; Auto user code ; Off ; On ;
; Configuration device ; Epcs4 ; Auto ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Use configuration device ; On ; On ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+------------------------------------------------+
; Assembler Encrypted IP Cores Summary ;
+--------+------------------------+--------------+
; Vendor ; IP Core Name ; License Type ;
+--------+------------------------+--------------+
; Altera ; Signal Tap (6AF7 BCE1) ; Licensed ;
; Altera ; Signal Tap (6AF7 BCEC) ; Licensed ;
+--------+------------------------+--------------+
+--------------------------------------------+
; Assembler Generated Files ;
+--------------------------------------------+
; File Name ;
+--------------------------------------------+
; D:/Electronics/MPU401 Core DE1/DE1_TOP.sof ;
; D:/Electronics/MPU401 Core DE1/DE1_TOP.pof ;
+--------------------------------------------+
+----------------------------------------------------------------------+
; Assembler Device Options: D:/Electronics/MPU401 Core DE1/DE1_TOP.sof ;
+----------------+-----------------------------------------------------+
; Option ; Setting ;
+----------------+-----------------------------------------------------+
; Device ; EP2C20F484C7 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x00543ED5 ;
+----------------+-----------------------------------------------------+
+----------------------------------------------------------------------+
; Assembler Device Options: D:/Electronics/MPU401 Core DE1/DE1_TOP.pof ;
+--------------------+-------------------------------------------------+
; Option ; Setting ;
+--------------------+-------------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x05991993 ;
; Compression Ratio ; 2 ;
+--------------------+-------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Jun 19 02:42:09 2018
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DE1_TOP -c DE1_TOP
Critical Warning (138069): Setting INCREMENTAL_COMPILATION to "OFF" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to "ON" instead.
Critical Warning (15685): M4K memory block WYSIWYG primitive "ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|altsyncram_7ub2:altsyncram1|ram_block3a0" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|altsyncram_7ub2:altsyncram1|ram_block3a2" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|altsyncram_7ub2:altsyncram1|ram_block3a4" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "ram:ram_inst|altsyncram:altsyncram_component|altsyncram_9dg1:auto_generated|altsyncram_7ub2:altsyncram1|ram_block3a6" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "internal_ram:internal_ram_inst|altsyncram:altsyncram_component|altsyncram_8eg1:auto_generated|altsyncram_bob2:altsyncram1|ram_block3a0" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a0" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a9" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a18" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a27" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a36" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a45" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a54" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a63" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a72" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a81" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a90" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a99" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Critical Warning (15685): M4K memory block WYSIWYG primitive "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_ne54:auto_generated|ram_block1a108" utilizes the dual-port dual-clock mode with WYSIWYG parameter SAFE_WRITE = "VERIFIED_SAFE". However, this mode might not work in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 19 warnings
Info: Peak virtual memory: 507 megabytes
Info: Processing ended: Tue Jun 19 02:42:10 2018
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:02