Can Dynamatic be used for generating Verilog? #75
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Hi everyone, |
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Hi! Thanks for reaching out! We have plans to support Verilog in the near future yes. I am in fact currently working on a new RTL backend that will be able to produce the "glue" RTL code (i.e., the "top-level netlist" connecting standard dataflow components with dataflow channels to implement the compiled kernel) in both VHDL and Verilog. Then we will port our standard dataflow components' Verilog implementations from the LLVM-IR-based version of Dynamatic. This will allow us to produce dataflow circuits fully in Verilog :) |
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Hi! Thanks for reaching out!
We have plans to support Verilog in the near future yes. I am in fact currently working on a new RTL backend that will be able to produce the "glue" RTL code (i.e., the "top-level netlist" connecting standard dataflow components with dataflow channels to implement the compiled kernel) in both VHDL and Verilog. Then we will port our standard dataflow components' Verilog implementations from the LLVM-IR-based version of Dynamatic. This will allow us to produce dataflow circuits fully in Verilog :)