ASIC Lab 3: Logic Synthesis

Prof. John Wawrzynek

TA: Kevin He, Kevin Anderson

Department of Electrical Engineering and Computer Science

College of Engineering, University of California, Berkeley

Overview

TBD

Acknowledgement

This lab is the result of the work of many EECS151/251 GSIs over the years including: Written By:

Nathan Narevsky (2014, 2017)
Brian Zimmer (2014)

Modified By:

John Wright (2015,2016)
Ali Moin (2018)
Arya Reais-Parsi (2019)
Cem Yalcin (2019)
Tan Nguyen (2020)
Harrison Liew (2020)
Sean Huang (2021)
Daniel Grubb, Nayiri Krzysztofowicz, Zhaokai Liu (2021)
Dima Nikiforov (2022)
Roger Hsiao, Hansung Kim (2022)
Chengyi Lux Zhang, (2023)
Kevin Anderson, Kevin He (Sp2024)