generate.va

// This file is generated by the VA_GEN .

`include "constants.vams"
`include "disciplines.vams"

module Va_TimeGen_1(VDD, GND, CLK,   signal_1, signal_2);
	input VDD, GND, CLK ;
    electrical VDD, GND, CLK ;



    output [7:0] signal_1 ;
    electrical [7:0] signal_1 ;

    output  signal_2 ;
    electrical  signal_2 ;




    integer signal_signal_1 ;
    integer signal_signal_2 ;

    
    integer count_signal_1 ;
    integer count_signal_2 ;


    integer wave_signal_1 [0:3] = {  0, 1, 2, 3, } ;
    integer wave_signal_2 [0:3] = {  0, 1, 0, 1, } ;



	integer count = 0;
	integer clock = 0;
	integer flag_clk ;
    
    genvar i ;

//       ___                   __                                         
//      /\_ \                 /\ \                                        
//   ___\//\ \     ___     ___\ \ \/'\               __      __    ___    
//  /'___\\ \ \   / __`\  /'___\ \ , <    _______  /'_ `\  /'__`\/' _ `\  
// /\ \__/ \_\ \_/\ \L\ \/\ \__/\ \ \\`\ /\______\/\ \L\ \/\  __//\ \/\ \ 
// \ \____\/\____\ \____/\ \____\\ \_\ \_\/______/\ \____ \ \____\ \_\ \_\
//  \/____/\/____/\/___/  \/____/ \/_/\/_/         \/___L\ \/____/\/_/\/_/
//                                                   /\____/    	
//                                                   \_/__/ 
	
	// Clock-Generator
	analog begin
		@(initial_step)	begin

			count = 0 ;
			clock = 0 ;
			flag_clk = 0 ;

            signal_signal_1 = 0 ;
            signal_signal_2 = 0 ;

            count_signal_1 = 0 ;
            count_signal_2 = 0 ;


		end

		@( cross( V(CLK,GND)- V(VDD,GND), +1 ) ) begin	
			clock = 1 ;
			count = count + 1 ;
			if(count >= 100 ) count = 0 ;
		end

		@( cross( clock - 1 , +1) )  begin
			if(clock != 0) clock = 0 ;
			flag_clk = 1 ;	
		end

	end

//  __      __                                             ____                      
// /\ \  __/\ \                                           /\  _`\                    
// \ \ \/\ \ \ \     __     __  __     __    ____         \ \ \L\_\     __    ___    
//  \ \ \ \ \ \ \  /'__`\  /\ \/\ \  /'__`\ /',__\  _______\ \ \L_L   /'__`\/' _ `\  
//   \ \ \_/ \_\ \/\ \L\.\_\ \ \_/ |/\  __//\__, `\/\______\\ \ \/, \/\  __//\ \/\ \ 
//    \ `\___x___/\ \__/.\_\\ \___/ \ \____\/\____/\/______/ \ \____/\ \____\ \_\ \_\
//     '\/__//__/  \/__/\/_/ \/__/   \/____/\/___/            \/___/  \/____/\/_/\/_/


	// Waves-Generator
	analog begin

		@( cross( flag_clk - 1 , +1) )  begin
			flag_clk = 0 ;

            signal_signal_1 = wave_signal_1[ count_signal_1 % 4 ] ;
            signal_signal_2 = wave_signal_2[ count_signal_2 % 4 ] ;

            count_signal_1 = count_signal_1 + 1 ;
            count_signal_2 = count_signal_2 + 1 ;


		end


	end

//                __                     __      
//               /\ \__                 /\ \__   
//   ___   __  __\ \ ,_\  _____   __  __\ \ ,_\  
//  / __`\/\ \/\ \\ \ \/ /\ '__`\/\ \/\ \\ \ \/  
// /\ \L\ \ \ \_\ \\ \ \_\ \ \L\ \ \ \_\ \\ \ \_ 
// \ \____/\ \____/ \ \__\\ \ ,__/\ \____/ \ \__\
//  \/___/  \/___/   \/__/ \ \ \/  \/___/   \/__/
//                          \ \_\                
//                           \/_/                

	// Signal-Output
	analog begin


        for(i=0; i<8; i=i+1) begin
            V( signal_1[i] ) <+ transition( V(VDD,GND)*((signal_signal_1&(1<<i))>>i), 0, 0 ) ;
        end
        

        for(i=0; i<1; i=i+1) begin
            V( signal_2 ) <+ transition( V(VDD,GND)*((signal_signal_2&(1<<i))>>i), 0, 0 ) ;
        end
        


	end


endmodule